HIGH PERFORMANCE, LOW POWER ARCHITECTURE OF 5- STAGE FIR FILTER USING MODIFIED COMPRESSOR WITH MONTGOMERY MULTIPLIER

Abstract

The digital world continues to witness an unprecedented growth in view of the technological
advancements in the field of Digital Signal Processing (DSP). The increased usage of digital
applications along with the tremendous evolution of Very Large Scale Integration (VLSI)
technology over a few epochs has led to the development of enhanced algorithms and
architectures for DSP systems that augur to meet the demands of a wide variety of applications in
this expanding horizon of the signal processing sector. Finite Impulse Response (FIR) digital
filter is the most potent and frequently used component in various signal processing and image
processing applications. Since the intricacy of implementation grows with the filter order and the
precision of computation, real-time realization of these filters with desired level of accuracy and
less area-delay-power complexity is a challenging task.