DESIGN AND IMPLEMENTATION OF HISTOGRAM ESTIMATION ARCHITECTURES FOR 8X8 IMAGE

Abstract

Histogram estimation designs for evaluating sampled data have recently gained popularity and have found several applications in image processing, communications, computer vision, and pattern recognition, among other fields. As part of this study, the suggested
histogram estimation architecture is utilised to count the bin values. Additionally, the architecture is implemented on an Application Specific Integrated Circuit (ASIC) platform and also on an FPGA platform to demonstrate its functionality (FPGA). Through the use of
MATLAB, the input 8x8 picture is translated into binary samples, and these values are then passed on to the input of the verilog code. It is the modelsim programme that is used to generate the simulation results for the suggested design. For the 8x8 image, we evaluate
the performances of both existing and proposed architectures, and to obtain the performance of ASIC, the architectures are implemented in cadence encounter using 180nm technology. The percentage reduction of area power and delay is 17.6 percent, 32
percent, and 18 percent, respectively for the existing and proposed architectures. In addition, the virtex-6 device reduces the consumption of lookup tables, slice registers, and the amount of flipflops per unit of time. Optimal Bin Counter, Application Specific Integrated Chip, Field Programmable Gate Array, Dual port Read Only Memory, Histogram estimate are some of the terms used in
this paper.